Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

CROSS REFERENCES TO RELATED APPLICATION

The present application is a Reissue Continuation Application ofapplication Ser. No. 13/687,996, filed Nov. 28, 2012, which is a ReissueContinuation Application of reissue application Ser. No. 13/340,130,filed Dec. 29, 2011, now U.S. Pat. No. RE43,912, which is a ReissueApplication of application Ser. No. 12/289,571, filed Oct. 30, 2008, nowU.S. Pat. No. 7,696,788, issued Apr. 13, 2010, which is a ContinuationApplication of Continuation application Ser. No. 11/808,975, filed Jun.14, 2007, which is a continuation of Parent application Ser. No.11/070,205, filed Mar. 3, 2005, now U.S. Pat. No. 7,274,210, issued Sep.25, 2007.

The present invention contains subject matter related to Japanese PatentApplication JP 2004-067489 filed in the Japanese Patent Office on Mar.10, 2004, the entire contents of which is also incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit,and, more particularly, to a semiconductor integrated circuit achievinga reduction of power consumption by using a transistor having a highthreshold voltage to cut the supply of power to an unused circuit.

2. Background Art

The power supply voltage of semiconductor integrated circuits has fallenyear by year along with the reduction of power consumption and theminiaturization of processing dimensions. When a signal amplitudebecomes small due to the reduction of the power supply voltage, thethreshold voltage of a transistor becomes high relative to the signalamplitude, so an on current of the transistor decreases and a delayincreases. For this reason, the threshold voltage of the transistor alsomust be made lower along with the power supply voltage. However, aleakage current in an off state increases when the threshold voltage ofthe transistor is lowered, so there is the disadvantage that reductionof the power consumption is obstructed.

As technology preventing the increase of such leakage current, the“multi-threshold complementary metal oxide semiconductor” (MTCMOS)circuit technology is known. In a MTCMOS, for example, a transistorswitch having a high threshold voltage is arranged in a power line ofeach circuit block performing a specific function. When the circuitblock becomes unused in state, the transistor switch is set to the offposition and the leakage current flowing through each transistor in thecircuit block is shut off. By this, useless leakage current flowingthrough unused circuit blocks can be greatly reduced.

SUMMARY OF THE INVENTION

In the design of semiconductor integrated circuits incorporating MTCMOStechnology, however, the layout design for arranging the transistorswitches in the power lines is generally carried out manually. Forexample, the arrangement and interconnect lines of circuit cells insideeach circuit block performing a specific function are automaticallydesigned by a CAD device for each circuit block, then a transistorswitch is manually arranged in the power line at the outside of thecircuit block. For this reason, there are the disadvantages that theload of the design work increases and the development period of theproduct becomes long.

Further, along with the reduction of the power supply voltage, a slightvoltage drop occurring in a resistive component of the power line startsto exert a large influence upon the delay of the signal. Namely, thelower the power supply voltage, the smaller the margin of the signalamplitude with respect to the threshold voltage of a transistor, so alarge signal delay occurs even if the drop of the power supply voltageis small.

When a transistor switch is arranged in a power line under such asituation, the voltage drop due to this is further added, so the aboveproblem becomes more serious. Especially, the signal delay at the centerof the circuit block where the distance from the external power linebecomes long becomes large. As a result, there is the problem that evenif the circuit block normally operates by itself, it no longer operateswhen a transistor switch is arranged in the external power line.Further, when the circuit block is further connected to a block of ahigher level, there is the problem that the requested timing can nolonger be satisfied.

There is a need for providing a semiconductor integrated circuit able toreduce the load of the layout design for arranging the power switchesand able to reduce the influence of the voltage drop occurring in powerswitches exerted upon signal delay.

According to one embodiment of the present invention, there is provideda semiconductor integrated circuit including a plurality of circuitcells; a plurality of groups of power lines arranged in stripe shapes; aplurality of groups of branch lines branching from the groups of powerlines and supplying power to at least one of the circuit cells; and apower switch cell arranged in at least one group of branch lines andturning on or off the supply of power to the circuit cell in accordancewith an input control signal.

According to one embodiment of the present invention, a plurality ofgroups of power lines are arranged in stripe shapes, and power issupplied to the circuit cells by a plurality of groups of branch linesbranching from the groups of power lines. The power switch cell arrangedin the group of branch lines controls the supply of power to the circuitcell.

For this reason, the power switch cells are arranged dispersed in thearea of arrangement of the circuit cells. The supply of power by thepower switch cells is finely controlled for each relatively small numberof circuit cells. Due to this, in comparison with the method ofproviding a power switch for each circuit block, the voltage drop of thepower by the power switch becomes small and the degree of freedom ofarrangement of the power switch cells is raised.

Preferably, each group of branch lines is formed extending in adirection forming a predetermined angle with the group of power linesfrom which the group of branch lines branch. Due to this, the symmetryof the interconnect line structures of the power rises.

Further, preferably, each power switch cell includes at least onetransistor arranged in at least one branch line included in the group ofbranch lines and turning on or off in accordance with the controlsignal. This transistor has a drive capability according to the powerconsumption of the circuit cell to which power is supplied through thebranch line when the transistor is in the on state. For example, thelarger the power consumption, the larger the drive capability.

By setting the drive capability of the switch transistor to a suitablemagnitude in accordance with the power consumption of the circuit cellto which power is supplied through the switch transistor, in comparisonwith the case where the drive capability of the transistor switch isuniformly set, it becomes possible to reduce the circuit area and theleakage current while suppressing the reduction of the power supplyvoltage.

At least part of each power switch cell may be included in an area undera group of power lines. In this case, the group of branch lines mayinclude a via interconnect line branching from a power line of the groupof power lines and extending to the lower layer. Due to this, thedensity of arrangement of the circuit cells is improved.

Each power switch cell may include a first interconnect line connectedto two branch lines supplying power to the circuit cell, facing eachother across the power switch cell, and extending in opposite directionsfrom each other; a second interconnect line connected to a branch linebranching from a power line of the group of power lines; and a switchcircuit connected between the first interconnect line and the secondinterconnect line and turning on or off in accordance with the controlsignal as well.

The power switch cell may include a third interconnect line connected toa branch line supplying power to the circuit cell; a fourth interconnectline connected to a branch line, the branch line branching from a powerline of the group of power lines and extending in an opposite directionof the branch line connected to the third interconnect line; and aswitch circuit connected between the third interconnect line and thefourth interconnect line and turning on or off in accordance with thecontrol signal as well.

The group of branch lines may include a first branch line and a secondbranch line connected to a power line of the group of power lines aswell. In this case, the power switch cell may turn on or off aconnection between the first branch line and the second branch line inaccordance with the control signal as well. Further, the plurality ofcircuit cells may include a first circuit cell supplied with power fromthe first branch line and a second circuit cell supplied with power fromthe second branch line as well.

In this case, the first branch line and the second branch line may beformed in a same interconnect line layer side by side or may be formedin different interconnect line layers and facing each other.

Further, in this case, each power switch cell may comprise a fifthinterconnect line connected to the first branch line; a sixthinterconnect line connected to the second branch line; and a switchcircuit connected between the fifth interconnect line and the sixthinterconnect line and turning on or off in accordance with the controlsignal.

According to one embodiment of the present invention, the degree offreedom of arrangement of the power switch cells becomes high, andautomatic design of the layout by the CAD device can be easily realized,so the load of the layout design can be reduced.

Further, the voltage drop of the power due to the power switch cells canbe suppressed, so the influence of the voltage drop occurring in thepower switch cells exerted upon the signal delay can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

FIG. 1 is a view of an example of the configuration of a semiconductorintegrated circuit according to a first embodiment;

FIG. 2 is a view of an example of a layout of the semiconductorintegrated circuit according to the first embodiment;

FIG. 3 is an enlarged view of the example of layout of the semiconductorintegrated circuit according to the first embodiment;

FIG. 4 is a view of an example of the configuration of a circuit cellaccording to a second embodiment;

FIG. 5 is a view of an example of the configuration of a power switchcell according to the second embodiment.

FIG. 6 is a view of an example of the layout of the semiconductorintegrated circuit according to the second embodiment;

FIG. 7 is a view of an example of the configuration of a power switchcell according to a third embodiment;

FIG. 8 is a view of an example of the layout of the semiconductorintegrated circuit according to the third embodiment;

FIG. 9 is a view of an example of the configuration of a power cutofftype circuit cell according to a fourth embodiment;

FIG. 10 is a view of an example of the configuration of a constantlypowered circuit cell according to the fourth embodiment;

FIG. 11 is a view of an example of the configuration of a power switchcell according to the fourth embodiment;

FIG. 12 is a view of an example of the layout of the semiconductorintegrated circuit according to the fourth embodiment;

FIG. 13 is a view of an example of the arrangement of a power cutofftype circuit cell and a constantly powered circuit cell;

FIG. 14 is a view of an example of the configuration of a power cutofftype circuit cell according to a fifth embodiment;

FIG. 15 is a view of an example of the configuration of a constantlypowered circuit cell according to the fifth embodiment;

FIG. 16 is a view of an example of the configuration of a power switchcell according to the fifth embodiment;

FIG. 17 is a view of an example of the layout of a semiconductorintegrated circuit according to the fifth embodiment;

FIG. 18 is a view of an example of a plurality of power switch cellshaving different drive capabilities according to a sixth embodiment;

FIG. 19 is a first view of an example of combining a two-interconnectline type structure and a three-interconnect line type structure; and

FIG. 20 is a second view of an example of combining a two-interconnectline type structure and a three-interconnect line type structure.

BEST MODE FOR WORKING THE INVENTION

Below, an explanation will be given of six embodiments of the presentinvention by referring to the drawings.

First Embodiment

FIG. 1 is a view of an example of the configuration of a semiconductorintegrated circuit according to a first embodiment of the presentinvention. In the figure, interconnect lines relating to the power andcircuit cells connected to them are schematically illustrated.

The semiconductor integrated circuit shown in FIG. 1 has a plurality ofgroups of power lines PL1, a plurality of groups of power lines PL2, aplurality of groups of branch lines BL1 and BL2, a plurality of circuitcells 10, a plurality of power switch cells 20, a circuit block 30, anda plurality of power input cells 41 and 42.

Note that the groups of power lines PL1 are embodiments of the groups ofpower lines of the present invention, the groups of branch lines BL2 areembodiments of the groups of branch lines of the present invention, thecircuit cells 10 are embodiments of the circuit cells of the presentinvention, and the power switch cells 20 are embodiments of the powerswitch cells of the present invention.

The groups of power lines PL1 are arranged in stripe shapes in theexample of FIG. 1, and they are arranged in parallel at substantiallyequal intervals. The groups of power lines PL2 are arranged in stripeshapes in a direction perpendicular to the groups of power lines PL1. Inthe example of FIG. 1, they are arranged in parallel at substantiallyequal intervals. These stripe shaped groups of power lines PL1 andstripe shaped groups of power lines PL2 intersect each other and formlattice stripe shaped power line patterns.

The groups of power lines PL1 and PL2 have power lines VDD and VSS. Atintersecting points of the lattice stripe shaped power line patterns,the power lines VDD and the power lines VSS of the groups of power linesPL1 and PL2 are connected to each other.

In the lattice stripe shaped power line patterns, power input cells 41and 42 are connected to the groups of power lines PL1 and PL2 of arectangular frame. The power line VSS is connected to the power inputcell 41, and the power line VDD is connected to the power input cell 42.

The power supply voltage is supplied through these power input cells 41and 42 to the power lines VSS and VDD from the outside of thesemiconductor integrated circuit.

The groups of branch lines BL1 and BL2 branch from the groups of powerlines PL1 and supply power to the basic units of the circuit in thesemiconductor integrated circuit, that is, the circuit cells 10.Further, the groups of branch lines BL1 and BL2 are formed extending indirections forming predetermined angles with the groups of power linesPL1. For example, as shown in FIG. 1, they are formed extending indirections perpendicular to the groups of power lines PL1.

A plurality of such groups of branch lines branch from one group ofpower lines PL1. A plurality of circuit cells 10 are connected to thegroups of branch lines. The circuit cells 10 included in thesemiconductor integrated circuit are basically supplied with power fromthese groups of branch lines. Note that the circuits not needing cutoffof power since they are always operating, etc., include circuitsdirectly supplied with power from the groups of power lines withoutgoing through the groups of branch lines, for example, the circuit block30 shown in FIG. 1.

Each group of branch lines BL1 has two branch lines (VDDA and VSSA). Thebranch line VDDA is connected to the power line VDD, while the branchline VSSA is connected to the power line VSS. On the other hand, eachgroup of branch lines BL2 has two branch lines (VDDB and VSSB). Thebranch line VDDB is connected to the power line VDD, while the branchline VSSB is connected to the power line VSS. The difference of thegroups of branch lines BL1 and BL2 resides in the insertion ornon-insertion of the power switch cell 20. Namely, the power switch cell20 only is inserted in the group of branch lines BL2.

The power switch cell 20 receives as input a not illustrated controlsignal and accordingly turns on or off the supply of power to thecircuit cell 10 connected to the group of branch lines BL2. For example,the power switch cell 20 includes a switch transistor. The switchtransistor is arranged in at least one branch line of the group ofbranch lines BL2 and turns on

In the case of a MTCMOS type semiconductor integrated circuit, a highthreshold voltage MOS transistor is used for this switch transistor. Forexample, when cutting the branch line VSSB in accordance with thecontrol signal, a high threshold voltage n-type MOS transistor is usedas the switch transistor. When cutting the branch line VDDB inaccordance with the control signal, a high threshold voltage p-type MOStransistor is used.

FIG. 2 is a view of an example of the layout of a semiconductorintegrated circuit according to the present embodiment. In FIG. 2, thereference numerals “40” indicate input/output use cells including powerinput cells 41 and 42. Other than this, the same notations in FIG. 1 andFIG. 2 indicate the same components.

A plurality of input/output use cells 40 are arranged in lines on thefour sides of a rectangular semiconductor chip on which a semiconductorintegrated circuit is formed. Lattice stripe shaped power line patternsare formed inside the semiconductor chip surrounded by theseinput/output use cells 40.

The inside of the lattice stripe shaped power line patterns may beroughly divided into a non-power cutoff area A1, a power cutoff area A2,and other areas. In the non-power cutoff area A1, a circuit cell 10connected to the group of branch lines BL1 is arranged. In the powercutoff area A2, a circuit cell 10 connected to the group of branch linesBL2 is arranged. In the other areas, circuit cells not connected to thegroups of branch lines BL1 and BL2 are arranged. It is possible tofreely determine ranges of the power cutoff areas A1 and A2 shown inFIG. 2 by selecting insertion or non-insertion of a power switch cell 20in each group of branch lines.

FIG. 3 is an enlarged view of an example of the layout of thesemiconductor integrated circuit according to the present embodiment.The same notations in FIG. 1 and FIG. 3 indicate the same components.

In the example of FIG. 3, part of each power switch cell 20 is includedin an area under the group of power lines PL1. Interconnect linesbranching from the group of power lines PL1 to each power switch cell 20include, for example, via interconnect lines extending under the groupof power lines PL1.

As described above, according to the semiconductor integrated circuitaccording to the present embodiment, a plurality of groups of powerlines PL1 are arranged in stripe shapes, and power is supplied to thecircuit cells 10 by a plurality of groups of branch lines BL2 branchingfrom the groups of power lines PL1. Power switch cells 20 arranged inthe groups of branch lines BL2 turn on and off the supply of power tothe circuit cells 10.

For this reason, a plurality of power switch cells 20 are widelyarranged dispersed in the area where the circuit cells 10 can bearranged. It then becomes possible to finely control the supply of powerfor every relatively small number of circuit cells by each power switchcell 20.

Due to this, in comparison with the method of providing a power switchfor each large scale circuit block, the power current flowing througheach power switch cell 20 is reduced, and the power supply voltage dropcan be made small. As a result, the influence of the voltage dropoccurring in the power switch cells 20 exerted upon the signal delay canbe reduced.

Further, in comparison with the conventional method of arranging eachpower switch outside of the circuit block, the degree of freedom ofarrangement of the power switch cells 20 becomes high, and the powercutoff area can be freely determined as shown in FIG. 2 and FIG. 3. Dueto this, it becomes possible to easily realize automatic design of thelayout including the power switch cells 20, so the load of the designwork conventionally performed manually is reduced and the developmentperiod can be shortened.

Further, each group of branch lines BL2 is formed extending in adirection perpendicular to the group of power lines PL1 from which itbranches, so the symmetry of the interconnect line structures of thepower switch cell becomes high. Due to this, it becomes possible to moreeasily realize automatic design of a layout including the power switchcells 20.

Further, as shown in FIG. 3, by arranging each power switch cell 20 sothat at least a part thereof is included in an area under a group ofpower lines PL1, the areas under the groups of power lines PL1 can beeffectively utilized, so the circuit area can be reduced and the densityof arrangement of the circuit cells 10 can be raised.

Second Embodiment

Next, a second embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the second embodimentshows the configurations of the power switch cells and circuit cells andthe structures of the groups of branch lines connecting them in moredetail than the semiconductor integrated circuit according to the firstembodiment. The overall configuration, such as the arrangement of thegroups of power lines, is the same as that of the semiconductorintegrated circuit according to the first embodiment.

FIG. 4 is a view of an example of the configuration of a circuit cell 11according to the second embodiment of the present invention. The circuitcell 11 shown in FIG. 4 has an inverter circuit configured as a serialcircuit of a p-type MOS transistor Qp1 and an n-type MOS transistor Qn1and has interconnect lines L111 and L112 supplying power to thisinverter circuit. Note that while FIG. 4 shows an inverter circuit cellas one example, the circuit cells 11 explained in the present embodimentalso may include various other circuit cells used as basic circuits, forexample, NAND circuit cells.

The interconnect line L111 is connected to a branch line VSSB supplyinga potential VSS to the circuit cell 11. The interconnect line L111 hasthe same potential as the power line VSS when the power switch cell 21explained later is in the on state.

The interconnect line L112 is connected to a branch line VDDB branchingfrom the power line VDD. The interconnect line L112 has the samepotential as the power line VDD.

These interconnect lines L111 and L112 are formed at opposite sideportions of the rectangular circuit cell 11. The inverter circuit isarranged between these facing side portions.

FIG. 5 is a view of an example of the configuration of a power switchcell 21 according to the present embodiment. The power switch cell 21has a n-type MOS transistor Qn2 and interconnect lines L211 to L213. Then-type MOS transistor Qn2 is an embodiment of the switch circuit of thepresent invention, the interconnect line L211 is an embodiment of thefirst interconnect line of the present invention, and the interconnectline L212 is an embodiment of the second interconnect line of thepresent invention.

The interconnect line L211 is an interconnect line connected to twobranch lines VSSB supplying the potential VSS to different circuit cells11. These two branch lines VSSB extend in opposite directions to eachother across the power switch cell 21 as shown in FIG. 6. When the powerswitch cell 21 is on, power is supplied to the circuit cells 11connected to it.

The interconnect line L212 is connected to a branch line branching fromthe power line VSS. The interconnect line L212 has the same potential asthat of the power line VSS.

The interconnect line L213 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L213 has thesame potential as that of the power line VDD.

The n-type MOS transistor Qn2 has a drain that is connected to theinterconnect line L211, a source and a substrate that are connected tothe interconnect line L212, and a gate that receives as input a controlsignal Sc. The n-type MOS transistor Qn2 turns on or off in accordancewith the control signal Sc.

When the n-type MOS transistor Qn2 turns on, the interconnect line L211and the interconnect line L212 are connected, and power is supplied tothe circuit cell 11 connected to the two branch lines VSSB. When then-type MOS transistor Qn2 turns off, the interconnect line L211 and theinterconnect line L212 are disconnected, and the supply of power to thecircuit cell 11 is cut off.

The interconnect line L211 is formed at one side portion of therectangular power switch cell 2. A part thereof is sunken in an U-shapetoward the inside of the power switch cell 21. The interconnect lineL212 is formed in this U-shape recess. The interconnect line L213 isformed in the side portion facing to the interconnect line L211. Then-type MOS transistor Qn2 is arranged between the interconnect linesL211 and L213.

FIG. 6 is a view of an example of the layout of the semiconductorintegrated circuit according to the present embodiment. In the exampleof FIG. 6, groups of branch lines BL2-1 to BL2-4 branch from the groupsof power lines PL1. The respective groups of branch lines BL2-1 to BL2-4have branch lines VDDB and VSSB. All branch lines extend in directionsperpendicular to the groups of power lines PL1.

The groups of branch lines BL2-1 and BL2-2 are adjacent to each otherand share the branch line VSSB. The groups of branch lines BL2-3 andBL2-4 are adjacent to each other and share the branch line VSSB.

The groups of branch lines BL2-1 and BL2-3 branch from a common branchpoint of the groups of power lines PL1 and extend in opposite directionsto each other across a common power switch cell 21. The groups of branchlines BL2-2 and BL2-4 branch from a common branch point of the groups ofpower lines PL1 and extend in opposite directions to each other across acommon power switch cell 21.

Further, at least parts of the power switch cell 21 connected to thegroups of branch lines BL2-1 and BL2-3 and the power switch cell 21connected to the groups of branch lines BL2-2 and BL2-4 are included inareas under the groups of power lines PL1.

The interconnect line branching from the power line VSS to theinterconnect line L212 includes via interconnect lines CT2 branchingfrom the power line VSS and extending to the lower layer. The viainterconnect lines CT2 connect the power line VSS and the interconnectline L212 in the lower layer. The interconnect line branching from thepower line VDD to the interconnect line L213 includes via interconnectlines CT1 branching from the power line VDD and extending to the lowerlayer. The via interconnect lines CT1 connect the power line VDD and theinterconnect line L213 in the lower layer.

Further, these two power switch cells 21 are adjacent to each other, andinterconnect lines L211 of the two are electrically connected, andtherefore they function as two parallel connected switches. Accordingly,the n-type MOS transistors Qn2 of these two power switch cells 21 arecontrolled so as to turn on or off together by the same control signalSc.

As explained above, according to the present embodiment, in place of thetwo power lines (VDD, VSS) configuring the group of power lines PL1, twobranch lines (VDDB, VSSB) configuring the group of branch lines areconnected to the circuit cell 11, and therefore it is possible to use ageneral circuit cell used in a conventional semiconductor integratedcircuit for the circuit cell 11 of the present embodiment.

Further, since each power switch cell 21 is arranged so that at least apart thereof is included in an area under the group of power lines PL1,the density of arrangement of the circuit cells 11 can be raised.

Further, since adjacent groups of branch lines and power switch cellsshare interconnect lines, the circuit area can be reduced. In addition,the same effect can be exhibited by the same configuration as that ofthe semiconductor integrated circuit according to the first embodiment.

Note that, in the example of FIG. 6, since two power switch cells 21 areconnected in parallel, operation is possible even if reduced to onepower switch cell 21. Namely, it also is possible to control the powersupply of four groups of branch lines by one power switch cell 21.

Third Embodiment

Next, a third embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the third embodimentis obtained by changing parts of the configurations of the power switchcells and the interconnect line structures in the second embodimentexplained above. The overall configuration, such as the arrangement ofthe groups of power lines and the configuration of the circuit cells, isthe same as those of the semiconductor integrated circuits according tothe first and second embodiments.

FIG. 7 is a view of an example of the configuration of a power switchcell 22 according to the third embodiment of the present invention. Thepower switch cell 22 has a n-type MOS transistor Qn3 and interconnectlines L221 to L223. The n-type MOS transistor Qn3 is an embodiment ofthe switch circuit of the present invention, the interconnect line L221is an embodiment of the third interconnect line of the presentinvention, and the interconnect line L222 is an embodiment of the fourthinterconnect line of the present invention.

The interconnect line L221 is connected to a branch line VSSB1 supplyingthe potential VSS to the circuit cell 11. Unlike the interconnect lineL211 of the power switch cell 21 explained above, the number of branchlines connected to the interconnect line L221 is one.

The interconnect line L222 is connected to a branch line VSSB2 branchingfrom the power line VSS. The interconnect line VSSB2 extends in anopposite direction to the branch line VSSB1 as shown in FIG. 8. Namely,the interconnect line VSSB2 and the interconnect line VSSB1 extend inopposite directions to each other across the power switch cell 21.

The interconnect line L223 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L223 has thesame potential as that of the power line VDD.

The n-type MOS transistor Qn3 has a drain that is connected to theinterconnect line L221, a source and substrate that are connected to theinterconnect line L222, and a gate that receives as input a controlsignal Sc. The n-type MOS transistor Qn3 tunas on or off in accordancewith the control signal Sc. When the n-type MOS transistor Qn3 turns on,the interconnect line L221 and the interconnect line L222 are connected,and power is supplied to the circuit cell 11 connected to the branchline VSSB1. When the n-type MOS transistor Qn3 turns off, theinterconnect line L221 and the interconnect line L222 are disconnected,and the supply of power to the circuit cell 11 is cut off.

The interconnect line L222 starting from one corner of the rectangularpower switch cell 22 extends along the side of the rectangle. Theterminal end of the interconnect line L222 stops before reaching theother corner. The interconnect line L221 starting from that other cornerextends along the same side as the interconnect line L222 and, in themiddle of the side, bends toward the inside of the power switch cell 22in order to avoid the interconnect line L221. Then, it extends inparallel to the interconnect line L221 in a line from this bent portionto the terminal end. The interconnect line L223 is formed in the otherside portion facing the side on which the interconnect line L222 isformed. The n-type MOS transistor Qn3 is formed in an area between theinterconnect line L221 and the interconnect line L223.

FIG. 8 is a view of an example of the layout of the semiconductorintegrated circuit according to the present embodiment. In the exampleof FIG. 8, the groups of branch lines BL3-1 to BL3-4 branch from thegroup of power lines PL1. Each of the groups of branch lines BL3-1 toBL3-4 has branch lines VDDB and VSSB. Each branch line VSSB furtherincludes branch lines VSSB1 and VSSB2.

Each branch line VDDB is connected to a power line VDD through viainterconnect lines CT3. Each branch line VSSB2 is connected to a powerline VSS through via interconnect lines CT4. Each branch line VSSB1 isconnected to a branch line VSSB2 through a power switch cell 22. Thesebranch lines all extend in a direction perpendicular to the group ofpower lines PL1.

The groups of branch lines BL3-1 and BL3-2 are adjacent to each otherand share the branch lines VSSB (VSSB1 and VSSB2). The groups of branchlines BL3-3 and BL3-4 are adjacent to each other and share the branchlines. VSSB (VSSB1 and VSSB2).

The groups of branch lines BL3-1 and BL3-3 branch from a common branchpoint of the group of power lines PL1 and extend in opposite directionsto each other from this branch point. The groups of branch lines BL3-2and BL3-4 branch from a common branch point of the group of power linesPL1 and extend in opposite directions to each other from this branchpoint.

The power switch cells 22 inserted in the groups of branch lines BL3-1and BL3-2 are adjacent to each other and are electrically connected tothe interconnect line L221. For this reason, these two power switchcells 22 function as two switches connected in parallel. Accordingly,the n-type MOS transistors Qn3 of these two power switch cells 22 arecontrolled so as to turn on or off together by the same control signalSc. The same is also true for the two power switch cells 22 inserted inthe groups of branch lines BL3-3 and BL3-4 and controlled by the samecontrol signal Sc.

As explained above, according to the present embodiment, in the same wayas the second embodiment, in place of the two power lines (VDD, VSS)configuring the group of power lines PL1, the two branch lines (VDDB,VSSB) configuring the group of the branch lines are connected to eachcircuit cell 11, so it is possible to easily use general circuit cellsused in a conventional semiconductor integrated circuit for the circuitcells 11 of the present embodiment.

Further, of the two branch lines VSSB1 and VSSB2 extending in oppositedirections across the power switch cell 22, the branch line VSSB1 iscontrolled in power by the n-type MOS transistor Qn3, and the branchline VSSB2 is constantly supplied with power from the power line VSS.For this reason, it is also possible to arrange a constantly operatedcircuit cell 11 in an empty space between the group of power lines PL1and the power switch cell 22 as shown in FIG. 8 and supply power fromthe branch lines VSSB2 and VDDB.

Further, when there are no constantly operated circuit cells 11, it isalso possible that at least part of each power switch cell 22 isincluded in the are funder the group of power lines PL1. Due to this,the density of arrangement of the circuit cells 11 can be improved.

Further, the example of FIG. 8 is structured by two power switch cells22 connected in parallel, and therefore operation is possible even ifthese are reduced to one power switch cell 22. Namely, it is alsopossible to control the power supply of two groups of branch lines by asingle power switch cell 21.

Further, in the present embodiment, in the same way as the firstembodiment, the groups of branch lines and the power switch cellsadjacent to each other share interconnect lines, so the circuit area canbe reduced. Other than this, the same effect can be exhibited by thesame configuration as that of the semiconductor integrated circuitaccording to the first embodiment.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the fourth embodimentis obtained by changing the configuration of the semiconductorintegrated circuits according to the second and third embodiments inwhich the groups of branch lines were configured by two branch lines toa configuration in which the groups of branch lines are configured bythree branch lines so that circuit cells constantly needing power can befreely arranged at the groups of branch lines. The overallconfiguration, such as the arrangement of the groups of power lines, isthe same as that of the semiconductor integrated circuit according tothe first embodiment.

FIG. 9 is a view of an example of the configuration of a circuit cell 12according to the fourth embodiment of the present invention. The circuitcell 12 shown in FIG. 9 has an inverter circuit configured as a serialcircuit of a p-type MOS transistor Qp1 and a n-type MOS transistor Qn1and has interconnect lines L121 to L123 supplying power to this invertercircuit. Note that FIG. 9 shows an inverter circuit cell as an example,but the circuit cells 12 explained in the present embodiment also mayinclude various circuit cells used as basic circuits, for example, NANDcircuit cells.

The inverter circuit (Qp1, Qn1) is connected between the interconnectlines L121 and L123 and supplied with power from these interconnectlines. Accordingly, when a power switch cell 23 explained later is inthe off state, the supply of power to the inverter circuit is cut off.

Note that, in the example of FIG. 9, the substrate of the p-type MOStransistor Qp1 is connected to the interconnect line L123, and thesubstrate of the n-type MOS transistor Qn1 is connected to theinterconnect line L122. As will be explained later, the interconnectlines L122 and L123 are constantly connected to the power lines VSS andVDD, therefore, and regardless of cutoff or no cutoff of power, thesubstrate potentials of these MOS transistors can be held stable.

The interconnect line L121 is connected to a branch line VSSB3 supplyingthe power potential VSS to the circuit cell 12. The interconnect lineL121 has the same potential as that of the power line VSS when a powerswitch cell 23 explained later is in the on state.

The interconnect line L122 is connected to a branch line VSSB4 in thesame interconnect line layer as the branch line VSSB3. The interconnectline L122 has the same potential as that of the power line VSS.

The interconnect line L123 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L123 has thesame potential as that of the power line VDD.

The interconnect lines L122 and L123 are formed at opposite sideportions of the rectangular circuit cell 12. The interconnect line L121is formed at a position adjacent to the interconnect line L122 whileextending in a direction parallel to this. The inverter circuit isarranged in an area between these interconnect lines L121 and L123.

FIG. 10 is a view of an example of the configuration of a circuit cell13 according to the present embodiment. The circuit cell 13 shown inFIG. 10 has an inverter circuit configured as a serial circuit of ap-type MOS transistor Qp1 and a n-type MOS transistor Qn1 and hasinterconnect lines L131 to L133 supplying power to this invertercircuit.

Interconnect lines L131, L132, and L133 in the circuit cell 13correspond to the interconnect lines L121, L122, and L123 in the circuitcell 12 explained above. The structures of the two and the branch linesto which they are connected are the same.

The difference of the circuit cell 12 and the circuit cell 13 resides inthe interconnect lines supplying power to the inverter circuit (Qp1,Qn1). Namely, the circuit cell 12 is supplied with power from theinterconnect lines L121 and L123, and therefore the supply of power iscut off when the power switch cell 23 is off, but the circuit cell 13 issupplied with power from the interconnect lines L132 and L133, thereforepower is constantly supplied regardless of the state of the power switchcell 23.

FIG. 11 is a view of an example of the configuration of a power switchcell 23 according to the present embodiment. The power switch cell 23has a n-type MOS transistor Qn4 and interconnect lines L231 to L233. Then-type MOS transistor Qn4 is an embodiment of the switch circuit of thepresent invention, the interconnect line L231 is an embodiment of thefifth interconnect line of the present invention, and the interconnectline L232 is an embodiment of the sixth interconnect line of the presentinvention.

The interconnect line L231 is an interconnect line connected to thebranch line VSSB3 supplying power to the circuit cell 12. When then-type MOS transistor Qn4 is on, it has the same potential as that ofthe power line VSS.

The interconnect line L232 is connected to the branch line VSSB4branching from the power line VSS. The interconnect line L232 has thesame potential as that of the power line VSS.

The interconnect line L233 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L233 has thesame potential as that of the power line VDD.

The n-type MOS transistor Qn4 has a drain that is connected to theinterconnect line L231, a source and a substrate that are connected tothe interconnect line L232, and a gate that receives as input a controlsignal Sc. The n-type MOS transistor Qn4 turns on or off in accordancewith the control signal Sc.

When the n-type MOS transistor Qn4 turns on, the interconnect line L231and the interconnect line L232 are connected, and power is supplied tothe circuit cell 12 connected to the branch line VSSB3. When the n-typeMOS transistor Qn4 turns off, the interconnect line L231 and theinterconnect line L232 are disconnected, and the supply of power to thecircuit cell 12 is cut off.

The interconnect lines L232 and L233 are formed at opposite sideportions of the rectangular power switch cell 23. The interconnect-lineL231 is formed at a position adjacent to the interconnect line L232while extending in a direction parallel to this. The n-type MOStransistor Qn4 is arranged in the area between these interconnect linesL231 and L233.

FIG. 12 is a view of an example of the layout of the semiconductorintegrated circuit according to the present embodiment. In the exampleof FIG. 12, the groups of branch lines BL4-1 to BL4-4 branch from thegroup of power lines PL1. The respective groups of branch lines BL4-1 toBL4-4 have branch lines VDDB, VSSB3, and VSSB4. Note that the branchline VSSB3 is not directly connected to the power line VSS, but isconnected to the power line VSS through the branch line VSSB4 when thepower switch cell 23 is on. Further, all of these branch lines extend indirections perpendicular to the group of power lines PL1 and are formedin the same interconnect line layer side by side.

The groups of branch lines BL4-1 and BL4-2 are adjacent to each otherand share the branch line VSSB4. The groups of branch lines BL4-3 andBL4-4 are adjacent to each other and share the branch line VSSB4.

The groups of branch lines BL4-1 and BL4-3 branch from a common branchpoint of the group of power lines PL1 and extend in opposite directionsto each other across a common power switch cell 23. The groups of branchlines BL4-2 and BL4-4 branch from a common branch point of the group ofpower lines PL1 and extend in opposite directions to each other across acommon power switch cell 23.

Further, at least parts of both of the power switch cell 23 connected tothe groups of branch lines BL4-1 and BL4-3 and the power switch cell 23connected to the groups of branch lines BL4-2 and BL4-4 are included inareas under the group of power lines PL1.

The interconnect line branching from the power line VSS to theinterconnect line L232 includes via interconnect lines CT6 branchingfrom the power line VSS and extending to the lower layer. The viainterconnect lines CT6 connect the power line VSS and the interconnectline L232 in the lower layer. The interconnect line branching from thepower line VDD to the interconnect line L233 includes via interconnectlines CT5 branching from the power line VDD and extending to the lowerlayer. The via interconnect line CT5 connects the power line VDD and theinterconnect line L233 in the lower layer.

FIG. 13 is a view of an example of the arrangement of the circuit cells12 and the circuit cells 13. As shown in FIG. 13, the circuit cells 12and 13 can be arranged mixed at any positions on the groups of branchlines.

As explained above, the present embodiment has a branch line VSSB3(first branch line) connected to a power line VSS through a switchcircuit (Qn4) of a power switch cell 23 and a branch line VSSB4 (secondbranch line) directly connected to the power line VSS without goingthrough the switch circuit (Qn4) and separately provides a circuit cell12 (first circuit cell) supplied with power from the branch line VSSB3and a circuit cell 13 (second circuit cell) supplied with power from thebranch line VSSB4.

For this reason, as shown in FIG. 13, circuit cells 12 able to be cutoff from the supply of power by the power switch cells 23 and circuitcells 13 constantly supplied with power can be arranged mixed at anypositions on the groups of branch lines. Due to this, it becomespossible to very freely arrange circuits to be cut off in power andcircuit to be constantly supplied with power, therefore the restrictionson the layout are reduced, and it becomes possible to realize automaticdesign of the layout including the power switch cells 23 by simplerprocessing.

Further, each power switch cell 23 is arranged so that at least a partthereof is included in an area under the group of power lines PL1, sothe density of arrangement of the circuit cells 12 and 13 can beimproved.

Further, in the present embodiment, the groups of branch lines adjacentto each other share branch lines. For example, in the example of FIG.13, the groups of branch lines BL4-5 and BL4-6, the groups of branchlines BL4-7 and BL4-8, and the groups of branch lines BL4-9 and BL4-10share branch lines VDDB. Further, the groups of branch lines BL4-6 andBL4-7, the groups of branch lines BL4-8 and BL4-9, and the groups ofbranch lines BL4-10 and BL4-11 share branch lines VSSB4.

For this reason, in comparison with the case where the branch lines areseparately provided, the circuit area can be reduced.

Other than this, the same effects can be exhibited by the sameconfiguration as the semiconductor integrated circuit according to thefirst embodiment.

Fifth Embodiment

Next, a fifth embodiment of the present invention will be explained.

The semiconductor integrated circuit according to the fifth embodimentis obtained by changing the branch lines formed in the same interconnectline layer side by side (first branch lines and second branch lines) inthe semiconductor integrated circuit according to the fourth embodimentto branch lines formed in different interconnect line layers facing eachother. The overall configuration, such as the arrangement of the groupsof power lines, is the same as that of the semiconductor integratedcircuit according to the first embodiment.

FIG. 14 is a view of an example of the configuration of a circuit cell14 according to the fifth embodiment of the present invention. Thecircuit cell 14 shown in FIG. 14 has an inverter circuit configured as aserial circuit of a p-type MOS transistor Qp1 and a n-type MOStransistor Qn1 and has interconnect lines L141 to L143 supplying powerto this inverter circuit. Note that FIG. 14 shows an inverter circuitcell as an example, but the circuit cells 14 explained in the presentembodiment also may include various circuit cells used as basiccircuits, for example, NAND circuit cells.

The inverter circuit (Qp1, Qn1) is connected between the interconnectlines L141 and L143 and supplied with power from these interconnectlines. Accordingly, when a power switch cell 24 explained later is inthe off state, the supply of power to the inverter circuit is cut off.Note that, in the example of FIG. 14, the substrate of the p-type MOStransistor Qp1 is connected to the interconnect line L143, and thesubstrate of the n-type MOS transistor Qn1 is connected to theinterconnect line L142. As will be explained later, the interconnectlines L142 and L143 are constantly connected to the power lines VSS andVDD, and therefore, regardless of cutoff or non-cutoff of power, thesubstrate potentials of these MOS transistors can be held stably.

The interconnect line L141 is connected to a branch line VSSB5 supplyingthe power potential VSS to the circuit cell 14. The interconnect lineL141 has the same potential as that of the power line VSS when a powerswitch cell 24 explained later is in the on state.

The interconnect line L142 is connected to a branch line VSSB6 in thelayer below the branch line VSSB5. The branch line VSSB6 is aninterconnect line branching from the power line VSS. The interconnectline L142 has the same potential as that of the power line VSS.

The interconnect line L143 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L143 has thesame potential as that of the power line VDD.

The interconnect lines L142 and L143 are formed at opposite sideportions of the rectangular circuit cell 12. The interconnect line L141is formed in a layer above the interconnect line L142 so as to face theinterconnect line L142. The inverter circuit is arranged in the areabetween the interconnect line L143 and the interconnect line L142.

FIG. 15 is a view of an example of the configuration of the circuit cell15 according to the present embodiment. The circuit cell 15 shown inFIG. 15 has an inverter circuit configured as a serial circuit of ap-type MOS transistor Qp1 and a n-type MOS transistor Qn1 and hasinterconnect lines L151 to L153 supplying power to this invertercircuit.

Interconnect lines L151, L152, and L153 in the circuit cell 15correspond to the interconnect lines L141, L142, and L143 in the circuitcell 14 explained above. The structures of the two and the branch linesto which they are connected are the same.

The difference of the circuit cell 14 and the circuit cell 15 resides inthe interconnect lines supplying power to the inverter circuit (Qp1,Qn1). Namely, the circuit cell 14 is supplied with power from theinterconnect lines L141 and L143, therefore the supply of power is cutoff when the power switch cell 24 is off, but the circuit cell 15 issupplied with power from the interconnect lines L152 and L153, so poweris always supplied regardless of the state of the power switch cell 24.

FIG. 16 is a view of an example of the configuration of the power switchcell 24 according to the present embodiment. The power switch cell 24has a n-type MOS transistor Qn5 and interconnect lines L241 to L243. Then-type MOS transistor Qn5 is an embodiment of the switch circuit of thepresent invention, the interconnect line L241 is an embodiment of thefifth interconnect line of the present invention, and the interconnectline L242 is an embodiment of the sixth interconnect line of the presentinvention.

The interconnect line L241 is connected to the branch line VSSB5supplying the potential VSS to the circuit cell 14. The interconnectline L241 has the same potential as that of the power line VSS when then-type MOS transistor Qn5 is on.

The interconnect line L242 is connected to the branch line VSSB6branching from the power line VSS. The interconnect line L242 has thesame potential as that of the power line VSS.

The interconnect line L243 is connected to the branch line VDDBbranching from the power line VDD. The interconnect line L243 has thesame potential as that of the power line VDD.

The n-type MOS transistor Qn5 has a drain that is connected to theinterconnect line L241, a source and a substrate that are connected tothe interconnect line L242, and a gate that receives as input a controlsignal Sc. The n-type MOS transistor Qn5 turns on or off in accordancewith the control signal Sc. When the n-type MOS transistor Qn5 turns on,the interconnect line L241 and the interconnect line L242 are connected,and power is supplied to the circuit cell 14 connected to the branchline VSSB5. When the n-type MOS transistor Qn5 turns off, theinterconnect line L241 and the interconnect line L242 are disconnected,and the supply of power to the circuit cell 14 is cut off.

The interconnect lines L242 and L243 are formed at opposite sideportions of the rectangular power switch cell 24. The interconnect lineL241 is formed in an interconnect line layer above the interconnect lineL242 so as to face the interconnect line L242. Note that at the centerportion of the side, the interconnect line L242 is sunken in an U-shapetoward the inside of the power switch cell 24. In this recess, viainterconnect lines CT8 (refer to FIG. 17) connecting the interconnectline L242 and the power line VSS are arranged. The n-type MOS transistorQn5 is arranged in the area between the interconnect line L241 and theinterconnect line L243.

FIG. 17 is a view of an example of the layout of the semiconductorintegrated circuit according to the present embodiment. In the exampleof FIG. 17, groups of branch lines BL5-1 to BL5-4 branch from the groupof power lines PL1. The respective groups of branch lines BL5-1 to BL5-4have branch lines VDDB, VSSB5, and VSSB6. Note that the branch lineVSSB5 is not directly connected to the power line VSS, but is connectedto the power line VSS through the branch line VSSB6 when the powerswitch cell 24 is on. Further, these branch lines extend in directionsperpendicular to the group of power lines PL1.

The groups of branch lines BL5-1 and BL5-2 are adjacent to each otherand share the branch lines VSSB5 and VSSB6. The groups of branch linesBL5-3 and BL5-4 are adjacent to each other and share the branch linesVSSB5 and VSSB6.

The groups of branch lines BL5-1 and BL5-3 branch from a common branchpoint of the group of power lines PL1 and extend in opposite directionsto each other across a common power switch cell 24. The groups of branchlines BL5-2 and BL5-4 branch from a common branch point of the group ofpower lines PL1 and extend in opposite directions to each other across acommon power switch cell 24.

Further, at least parts of both of the power switch cell 24 connected tothe groups of branch lines BL5-1 and BL5-3 and the power switch cell 24connected to the groups of branch lines BL5-2 and BL5-4 are included inan area under the group of power lines PL1.

The interconnect line branching from the power line VSS to theinterconnect line L242 includes via interconnect lines CT8 branchingfrom the power line VSS and extending to the lower layer. The viainterconnect lines CT8 connect the power line VSS and the interconnectline L242 in the lower layer. The interconnect line branching from thepower line VDD to the interconnect line L243 includes via interconnectlines CT7 branching from the power line VDD and extending to the lowerlayer. The via interconnect lines CT7 connect the power line VDD and theinterconnect line L243 in the lower layer.

Further, these two power switch cells 24 are adjacent to each other andare electrically connected to the interconnect line L241, so theyfunction as two parallel connected switches. Accordingly, the n-type MOStransistors Qns5 of these two power switch cells 24 are controlled so asto turn on or off together by the same control signal Sc.

As explained above, according to the present embodiment, the branchlines VSSB5 and VSSB6 are formed facing each other with a space betweenlayers, and therefore the circuit area can be reduced in comparison withthe case where they are formed in the same interconnect line layer.

Further, the power switch cells 24 are arranged so that at least partsthereof are included in the area under the group of power lines PL1, sothe density of arrangement of the circuit cells 14 and 15 can beimproved.

Further, in the example of FIG. 17, a structure where two power switchcells 24 connected in parallel is exhibited, and therefore operation ispossible even the reduced to one power switch cell 24. Namely, it isalso possible to control the supply of power of four groups of branchlines by one power switch cell 24.

Other than this, the same effect can be exhibited by the sameconfiguration as that of the semiconductor integrated circuit accordingto the fourth embodiment.

Sixth Embodiment

Next, a sixth embodiment of the present invention will be explained.

The switch transistor used in the power switch cell desirably has adrive capability as large as possible in order to reduce the drop of thepower supply voltage, but when this is made too large, the disadvantagesof an increase of the circuit area and leakage current are induced.

Therefore, in the semiconductor integrated circuit according to thepresent embodiment, the drive capabilities of the switch transistors areset in accordance with the power consumption of the circuit cells turnedon/off in supply of power according to this switch transistor. Forexample, the larger power consumption the circuit cells have, the largerdrive capabilities the switch transistors controlling the supply ofpower to the circuit cells have.

Namely, in the semiconductor integrated circuit according to the secondembodiment, the drive capability of the n-type MOS transistor Qn2 is setaccording to the power consumption of the circuit cell 11 connected tothe drain of the n-type MOS transistor Qn2 through the interconnect lineL211 of the power switch cell 21 and the branch line VSSB.

In the semiconductor integrated circuit according to the thirdembodiment, the drive capability of the n-type MOS transistor Qn3 is setaccording to the power consumption of the circuit cell 11 connected tothe drain of the n-type MOS transistor Qn3 through the interconnect lineL221 of the power switch cell 22 and the branch line VSSB1.

In the semiconductor integrated circuit according to the fourthembodiment, the drive capability of this n-type MOS transistor Qn4 isset according to the power consumption of the circuit cell 12 connectedto the drain of the n-type MOS transistor Qn4 through the interconnectline L231 of the power switch cell 23 and the branch line VSSB3.

In the semiconductor integrated circuit according to the fifthembodiment, the drive capability of this n-type MOS transistor Qn5 isset according to the power consumption of the circuit cell 14 connectedto the drain of the n-type MOS transistor Qn5 through the interconnectline L241 of the power switch cell 24 and the branch line VSSB5.

FIG. 18 is a view of an example of power switch cells 20A to 20Caccording to the sixth embodiment of the present invention. In theexample of FIG. 18, three types of power switch cells (20A to 20C)having different drive capabilities of the switch transistors areselectively used according to the magnitudes of the power consumptionsof the circuit cells when power is supplied. Namely, the power switchcell 20A having the maximum drive capability is used for the circuithaving the largest power consumption, the power switch cell 20B havingthe intermediate drive capability is used for the circuit having themedium power consumption, and the power switch cell 20C having theminimum drive capability is used for the circuit having the smallestpower consumption.

By setting the drive capabilities of the switch transistors at thesuitable magnitudes according to the power consumptions of the circuitcells supplied with power via the switch transistors in this way, incomparison with the case where the drive capabilities of the switchtransistors are uniformly set, the circuit area and the leakage currentcan be reduced while suppressing the drop of the power supply voltage.

While several preferred embodiments of the present invention wereexplained above, the present invention is not limited to only theseembodiments.

For example, it is also possible to use a two-interconnect line typepower structure in the second and third embodiments and athree-interconnect line type structure in the fourth and fifthembodiments in combination in a single semiconductor integrated circuit.FIG. 19 and FIG. 20 are views of an example of the combination of atwo-interconnect line type structure and a three-interconnect line typestructure. As described above, by combining a variety of interconnectline structures, the degree of freedom of the design is improved, andtherefore it becomes possible to select a more suitable interconnectline structure in accordance with the circuit to be designed.

Further, in the above embodiments, the number of power lines included inthe group of power lines is two, but the present invention is notlimited to this and may include three or more power lines.

Further, in the above embodiments, the example of disconnecting thebranch line connected to the power line VSS on the low voltage side bythe power switch cell is shown, but the present invention is not limitedto this. It is also possible to disconnect the branch line connected tothe power line VDD on the high voltage side by the power switch cell ordisconnect both of them by the power switch cell.

Further, in the above embodiments, in the lattice stripe shaped powerline patterns, the branch lines branch from only vertical stripe shapedpower lines, but the present invention is not limited to this and mayinclude also an area where the branch lines branch from horizontalstripe shaped power lines.

It should be understood by those skilled in the art that variousmodification, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

The invention claimed is:
 1. A semiconductor integrated circuitcomprising: a first branch line adapted to provide a potential to afirst circuit cell, a power line being at said potential; a secondbranch line adapted to provide said potential to a second circuit cell;and a third branch line adapted to provide another potential to saidfirst and second circuit cells, another power line being at said anotherpotential, wherein an electrical connection between said first branchline and said power line is controlled in accordance with a state of acontrol signal.
 2. A semiconductor integrated circuit as set forth inclaim 1, wherein said first circuit cell and said second circuit cellcan be arranged mixed at any positions on said first and second branchlines.
 3. A semiconductor integrated circuit as set forth in claim 1,wherein said potential is VSS.
 4. A semiconductor integrated circuit asset forth in claim 1, wherein an interconnection between said power lineand said second branch line is present regardless of said state of thecontrol signal.
 5. A semiconductor integrated circuit as set forth inclaim 1, wherein said another potential is VDD.
 6. A semiconductorintegrated circuit as set forth in claim 1, wherein said third branchline connects said another power line to said first and second circuitcells regardless of said state of the control signal.
 7. A semiconductorintegrated circuit as set forth in claim 1, further comprising: a powerswitch cell adapted to control said electrical connection between saidfirst branch line and said power line.
 8. A semiconductor integratedcircuit as set forth in claim 7, wherein said power switch cellcomprises: a first interconnect line connected to said first branchline; a second interconnect line connected to said power line; and aswitch circuit between said first interconnect line and said secondinterconnect line connecting said first interconnect line to said secondinterconnect line in accordance with said state of the control signal.9. A semiconductor integrated circuit comprising: power lines extendingalong a power line direction, the power line direction is other than abranch line direction; branch lines extending along the branch linedirection, a first one of the branch lines and a second one of thebranch lines are electrically connected to a first one of the powerlines; a first circuit cell between a third one of the branch lines andthe first one of the branch lines, the third one of the branch lines isbetween the first one of the branch lines and the second one of thebranch lines; a power switch cell that is controllable to provideelectrical connection and disconnection between a second one of thepower lines and the third one of the branch lines, the third one of thebranch lines and the first one of the branch lines are electricallyconnected directly to the first circuit cell; and a second circuit cellbetween the third one of the branch lines and the second one of thebranch lines, the second circuit cell is electrically connected directlyto the third one of the branch lines and the second one of the branchlines.
 10. A semiconductor integrated circuit as set forth in claim 9,wherein the power line direction is perpendicular to the branch linedirection.
 11. A semiconductor integrated circuit as set forth in claim9, wherein the power switch cell is in an area under the second one ofthe power lines.
 12. A semiconductor integrated circuit as set forth inclaim 9, further comprising: a first interconnect line that electricallyconnects a first one of the branch lines to a first one of the powerlines.
 13. A semiconductor integrated circuit as set forth in claim 12,further comprising: a second interconnect line that electricallyconnects a second one of the branch lines to the first one of the powerlines.